ADS1675高速模式下采样有问题，PLL倍频不上去。求大神帮忙看一下程序，若解决可有偿！
顶层程序：

– Company:
– Engineer:

– Create Date: 08:51:23 06/10/2019
– Design Name:
– Module Name: TOP - Behavioral
– Project Name:
– Target Devices:
– Tool versions:
– Description:

– Dependencies:

– Revision:
– Revision 0.01 - File Created
– Additional Comments:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_misc.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
– Uncomment the following library declaration if using
– arithmetic functions with Signed or Unsigned values
–use IEEE.NUMERIC_STD.ALL;

– Uncomment the following library declaration if instantiating
– any Xilinx primitives in this code.
–library UNISIM;
–use UNISIM.VComponents.all;

entity TOP is
port(
CS_1 : inout STD_LOGIC;
START : inout STD_LOGIC;
DRATE_0_1 : inout STD_LOGIC;
DRATE_1_1 : inout STD_LOGIC;
DRATE_2_1 : inout STD_LOGIC;
FPATH_1 : inout STD_LOGIC;
LL_CONFIG_1 : inout STD_LOGIC;
LVDS_1 : inout STD_LOGIC;
SCLK_SEL_1 : inout STD_LOGIC;
PDWN_1 : inout STD_LOGIC;

		  CLK_IN          : in     STD_LOGIC; 
		  
		  AD_CLK_1        : inout  STD_LOGIC;
		  
       AC_DRDY_1       : in     STD_LOGIC;
		  DRDY_1          : in     STD_LOGIC;     -- /DRDY_1  差分信号--DRDY
		  
		  AD_DOUT_1       : in     STD_LOGIC; 
		  DOUT_1          : in     STD_LOGIC;    --/DOUT_1
		  
		  AD_SCLK_1       : in     STD_LOGIC;
	     SCLK_1          : in     STD_LOGIC   --/SCLK_1	
	
);

end TOP;

architecture Behavioral of TOP is

COMPONENT fenpin
PORT(
clk_in : IN std_logic;
clk_out_8mhz_1 : out STD_LOGIC;
clk_out_8mhz : OUT std_logic
);
END COMPONENT;

COMPONENT ADC1675_1
Port ( AD_CLK : in STD_LOGIC;
CS : out STD_LOGIC;
START_1 : out STD_LOGIC;
DRATE_0 : out STD_LOGIC;
DRATE_1 : out STD_LOGIC;
DRATE_2 : out STD_LOGIC;
FPATH : out STD_LOGIC;
LL_CONFIG : out STD_LOGIC;
LVDS : out STD_LOGIC;
SCLK_SEL : out STD_LOGIC;
PDWN : out STD_LOGIC;

		   ADOUT         : out  std_logic_vector(23 downto 0);

– A : out STD_LOGIC_VECTOR(7 downto 0);
– B : out STD_LOGIC_VECTOR(7 downto 0);
– C : out STD_LOGIC_VECTOR(7 downto 0);
– D : out STD_LOGIC_VECTOR(7 downto 0);

		   ADC_DRDY      : in  STD_LOGIC;
--